Serial implementation of multipliers of 8 bits into the IC FPGA Acceleration Support Operation Multiplication As QDCT In Image Compression

Iman Ilmawan Muharam


 Multiplier is one of the most important parts in devices
that can aect device performance. Thus, high-speed mul-
tiplier and an ecient system is an important factor for
the designers of the microprocessors, microcontrollers and
other digital. As we know, the multiplication operation is
not dicult to do in decimal numbers. But, to perform
the operation in a binary number (which is used in digital
systems) is a very complex operation. In particular, if the
processing should be done in real time conditions, the algo-
rithm used in the multiplication operation to deal with high
throughput. In many implementations use the application
specic integrated circuits (ASICs). This is especially nec-
essary for image processing applications such as JPEG and
MPEG, etc., due to high development costs for ASIC, the
algorithm must be veried and optimized before implemen-
tation. FPGA allows a high degree of parallelism so as to in-
crease the resources available on the embedded FPGA. Ben-
et from the speed FPGA hardware and software
The purpose of this paper is to analyze a more optimal mul-
tiplication algorithm between Array Multiplier with Serial
multipliers are formed into a series of digital electronic and
implement these algorithms on a Spartan-3E FPGA IC by
minimizing the use of the resources of the FPGA device
used. Design and designing more eective than Multipliers
Serial Array multipliers for 4 bits, 6 bits and 8 bits views
of the resources used by parameters such as the Four In-
put LUTs, Occupied Slices, Bonded IOBs, Total Equivalent
Gate Count, Average Connection delay (ns ) and Pin Max-
imum delay (ns).

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